1. Field of the Invention
The present invention relates generally to electronic semiconductor package interconnections, and more particularly to a method and structure for joining electronic semiconductor chip packages.
2. Description of Related Art
As semiconductor devices become smaller and denser, it becomes increasingly important to join two semiconductor parts together, i.e., chip to chip, or chip to substrate, to reduce delay and improve performance. While existing processes can be used to join semiconductor chips having large feature sizes to a substrate, current technology does not provide an adequate method to make extremely small solder connections which can be used at a very early back end of the line ("BEOL") levels and later wiring levels. Controlled collapse chip connection ("C4") technology can be employed for first level assembly of chips on ceramic carriers, as disclosed in U.S. Pat. No. 5,729,896. However, C4 technology and ball limiting metallurgy is for much larger scale connections and feature sizes, rather than the micro connections of the present invention.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and structure to join semiconductor parts together.
Another object of the present invention is to provide a method and structure to join together semiconductor parts with extremely small electrical connections.
A further object of the present invention is to provide a method and structure to fabricate semiconductor chips and substrates separately and then join them together for functionality.
It is yet another object of the present invention to provide a method for joining multiple chips from different technologies together via a common back end for group functionality.
It is yet still another object of the present invention to provide a method and structure for joining semiconductor parts together which allows rework capability.